LSI Logic Optimizes Transceiver Speed and Power to Ease Design Of Communication ASICs With Modular Ultra HyperPHY(TM) Technology

Operating at 2.4 to 3.2 Gbps Per Channel With a Typical Power Dissipation Of 85 mW Per Channel at 3.125 Gbps, Ultra HyperPHY Offers Customers An Unparalleled Combination of Power and Performance for High-Density ASIC Designs

MILPITAS, Calif., May 1 /PRNewswire-FirstCall/ -- LSI Logic Corporation (NYSE: LSI - news) today announced the availability of its Ultra HyperPHY(TM) transceiver technology for next generation broadband transmission and networking ASICs requiring multiple high-speed data transfer channels operating from 2.4 Gbps to 3.2 Gbps. Offering an unparalleled combination of low power dissipation and high performance, the Ultra HyperPHY 0.11-micron CMOS modular architecture allows for customer specific ASIC designs to best meet the target system application. LSI Logic's Ultra HyperPHY technology provides an ideal solution to the backplane bandwidth bottleneck in high throughput SONET/SDH cross-connects and Dense Wavelength Division Multiplexing (DWDM) systems as well as in high bandwidth ATM and LAN switches.

"Our Ultra HyperPHY technology is designed to support the emerging needs of very high levels of integration and ultra high speed interfaces in ASICs for communication applications," said Dr. Hemant Thapar, senior vice president, Communications Technology, LSI Logic. "In a single chip, designers can include as many as 128 full duplex independent channels, thereby supporting interface bandwidths in excess of 800 Gbps. By combining the high performance, low power, small area and cost advantages of Ultra HyperPHY technology with the ease of use of LSI Logic's CoreWare® methodology and sophisticated modeling support for LSI Logic's HyperPHY cores, customers can easily and quickly get to market with system-level ASIC solutions."

System Approach Enables Complex Switch Box Designs

As more and more line cards are fit into a switch box, the distance a signal needs to travel across a backplane increases. With LSI Logic's Ultra HyperPHY transceivers, it is feasible to drive 3.2 Gbps signals across trace lengths of up to 39 inches (1 meter) on standard FR-4 material. The Ultra HyperPHY CML driver is programmable for both output swing and pre-emphasis, allowing the designer unprecedented flexibility in configuring the system for optimal performance.

LSI Logic system engineers can provide extensive backplane modeling support for systems using HyperPHY transceivers to predict end-to-end performance in a simulation-based "rapid prototyping" environment. This service to customers can minimize or even eliminate board problems due to high speed signaling, decreasing the time-to-market of the end product.

Support for Standard Interfaces and Backwards Compatibility

As a principal member of the Optical Internetworking Forum (OIF), LSI Logic has designed the Ultra HyperPHY transceiver to be fully compliant with the OIF SxI-5 electrical interface specification. Coupled with the modular HyperPHY architecture, LSI Logic supports the emerging SPI-5 and SFI-5 interfaces and their narrow band derivatives. The Ultra HyperPHY CML drivers and receivers are also compatible with the XAUI electrical standard for many applications.

Ultra HyperPHY transceivers can run in 1/2 rate and 1/4-rate modes, allowing bridging to previous generation systems operating at lower rates. The HyperPHY clock and data recovery design supports both un-encoded and 8B/10B encoded data streams.

HyperPHY Design Methodology Eases ASIC Designer Tasks

The Ultra HyperPHY cores provide physically separate transmit and receive (with clock recovery) functions. An application can have all transmit channels on one side of a die and all receive channels on another side of the die and still provide at-speed built-in-self-test (BIST), an important production test feature. The core modularity allows any combination of transmit and receive channels up to 128 on an ASIC. These HyperPHY "subsystems" are constructed by LSI Logic CoreWare engineers per customer direction.

"Backplanes and transceivers are used in almost all networking systems, including switches, routers, cross connects, add/drop multiplexers, DSLAMs and optical networking equipment, among others," said Sherry Garber, Senior Vice President, Semico Research Corporation. "The backplane, where all data is aggregated and switched, has become the most critical intra-system bandwidth bottleneck. LSI Logic is addressing these specific challenges and is delivering a technology with a substantial increase in performance and integration."

HyperPHY Transceiver Technology Family

Ultra HyperPHY in 0.11-micron CMOS represents the fourth generation of a continuing transceiver technology family from LSI Logic. The HyperPHY family also includes Standard HyperPHY, a transceiver technology that currently targets the data rates from 622 Mbps to 800 Mbps. Standard HyperPHY supports the SPI-4.2 physical layer interface, and coupled with the previously announced LSI Logic SPI-4.2 core, offers a complete SPI-4.2 protocol solution.

About LSI Logic Corporation

LSI Logic Corporation is a leading designer and manufacturer of communications, consumer and storage semiconductors for applications that access, interconnect and store data, voice and video. In addition, the company supplies storage network solutions for the enterprise. LSI Logic is headquartered at 1551 McCarthy Boulevard, Milpitas, CA 95035, 866-574-5741 (within U.S.), 408-954-3108 (outside U.S.), http://www.lsilogic.com .

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